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FDV304P - Digital FET/ P-Channel

Description

This P-Channel enhancement mode field effect transistors is produced using Fairchild's proprietary, high cell density, DMOS technology.

This very high density process is tailored to minimize on-state resistance at low gate drive conditions.

Features

  • -25 V, -0.46 A continuous, -1.5 A Peak. RDS(ON) = 1.1 Ω @ VGS = -4.5 V RDS(ON) = 1.5 Ω @ VGS= -2.7 V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.5V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model Compact industry standard SOT-23 surface mount package. SOT-23 Mark:304 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 D G S Absolute Maximum Ratings Symbol VDSS VGSS ID PD TJ,TSTG ESD Parameter Drain-Source Voltage Gate-Source Vol.

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Full PDF Text Transcription

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August 1997 FDV304P Digital FET, P-Channel General Description This P-Channel enhancement mode field effect transistors is produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize on-state resistance at low gate drive conditions. This device is designed especially for application in battery power applications such as notebook computers and cellular phones. This device has excellent on-state resistance even at gate drive voltages as low as 2.5 volts. Features -25 V, -0.46 A continuous, -1.5 A Peak. RDS(ON) = 1.1 Ω @ VGS = -4.5 V RDS(ON) = 1.5 Ω @ VGS= -2.7 V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.5V. Gate-Source Zener for ESD ruggedness.
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